The subject matter in this application is related to material in two other U.S. patent applications of Roy and Miller, entitled PARALLEL TESTING OF INTEGRATED CIRCUIT DEVICES USING CROSS-DUT AND WITHIN-DUT COMPARISONS, having Ser. No. 09/260,459 (P077), and EFFICIENT PARALLEL TESTING OF INTEGRATED CIRCUIT DEVICES USING A KNOWN GOOD DEVICE TO GENERATE EXPECTED RESPONSES, having Ser. No. 09/260,460 (P078), filed on the same date as this application and expressly incorporated herein by reference.
This invention is related to the testing of integrated circuit devices using a semiconductor tester, and more particularly to testing a number of devices in parallel using a single channel of the tester for greater efficiency and throughput.
Integrated circuit (IC) devices are an important part of almost every modern electronic or computer system. To reduce the manufacturing cost of such systems, the manufacturer expects each constituent IC device to be free of defects and to perform according to its specifications. Thus, it is not unusual to expect that every IC device is subjected to rigorous testing prior to being shipped to the system manufacturer.
It has been determined, however, that a significant portion of the total cost of producing an IC device can be attributed to its testing. That is because many modern IC devices perform complex functions, have a large number of inputs and outputs, and operate at high speeds. For instance, a 256 Mb memory device may have 16 data lines and 22 address lines. A simplistic approach to test such a device would be to write a known data value to each memory location, and then read from each location, and then compare the value read to the expected or written value to determine any errors. However, because of the large number of locations, each containing several bits, such a technique of testing each bit of each location is very time consuming. As a result, the field of test engineering has developed to create efficient techniques for detecting as many errors as possible while using the least number of test sequences.
A memory device may be tested using an automated semiconductor tester. FIG. 1 shows such a tester 108 having a number (N) of channels for parallel testing of a number of devices under test (DUTs) such as DUT 118. The tester 108 normally executes a test program and in response generates data and addresses on each channel which define a complex test sequence 106 engineered for testing the particular DUTs. Each channel of the tester 108 feeds a respective DUT so that a number of DUTs, corresponding to the number of channels, are tested simultaneously. A probe card (not shown) receiving all N channels delivers address and write data of the test sequence 106 to locations in N different DUTs simultaneously, while the DUTs are still part of a semiconductor wafer 116. The tester 108 then reads from those locations and performs a comparison with expected data it generates. The results of the comparison help determine whether a particular bit read from a location in a DUT is in error. The tester 108 performs the above read and write cycles many times with the same or different data patterns to verify as many locations of the DUTs as possible given time and budget constraints.
To increase throughput in terms of the number of DUTs tested per unit time, a larger tester may be built having more channels. Such a solution, however, could be prohibitively expensive. The tester is a complex and high speed machine, requiring much time and expense to modify or improve. Moreover, a single channel of a modern tester may comprise between 50 to 100 signal wires, such that increasing the number of channels between the tester and the probe card will make it physically impractical to connect all of the signal wires to the probe card. Therefore, a more efficient solution for increasing the throughput of an IC test system is needed.
Accordingly, an embodiment of the invention is directed to interface circuitry that essentially acts as a relay between the tester and a number of DUTs, where test vectors on each channel are fanned out to multiple DUTs. In general, the test vectors include stimuli, such as addresses, data values, and control signals, that are passed on to the DUTs while maintaining any timing constraints between the stimuli that were set up by the tester. The responses by the DUTs to these stimuli may then be collected by the interface circuitry and relayed back to the tester. If desired, the interface circuitry may be further enhanced with error detection capability based on the responses. For instance, the response from each DUT may be evaluated for internal consistency, by within-DUT and across-DUT comparisons, or it may be evaluated by comparison to expected responses received from the tester. The results of the comparison may then be provided back to the tester in summary or in detail form.
In a further embodiment, the interface circuitry features an input for receiving test data, expect data (test vectors), and control values from the tester. An output drives the test data into a number DUTs and then subsequently reads the data from the DUTs. Comparison circuitry provides error information in response to performing a comparison between data values read from each of the DUTs and expected data received from the tester. A storage area for the error information may be provided as part of the interface circuitry. The interface circuitry thus allows each channel of the conventional tester to be used to test not just a single DUT but a number of DUTs, preferably in parallel.
According to another embodiment of the invention, a system is disclosed for testing a number of DUTs, having a conventional tester with a number of sets of tester input/output (I/O) lines, the tester providing data values on each set of tester I/O lines for testing a single DUT, and a probe card having a number of probe elements for contacting a number of signal locations of two or more DUTs. The interface circuitry is aboard the probe card and has an input coupled to one of the sets of tester I/O lines and an output coupled to the probes. The interface circuitry transports data values from its input to its output, and performs a comparison using data values read from the DUTs to determine errors, if any, in the DUTs. Multiple DUTs may thus be tested by each channel of the tester, without disturbing the test sequence that was previously created to test a single DUT. The tester program inside the tester may be modified to read the error information through the same set of tester I/O lines after the test sequence has been completed.
In a particular embodiment, the results of the comparison (error information) are returned to the tester via the same channel in response to the tester requesting a read of previously written data. The tester program is modified to recognize that the error information received in response to its read request concerns a number of DUTs rather than just a single DUT.
In a particular embodiment, the DUTs are memory devices and the error information represents a difference between a data value read from each of the memory devices and an expected data value received by the interface circuitry from the tester for a pre-defined address/location.
These as well as other features and advantages of various embodiments of the invention can be better appreciated by referring to the claims, written description, and drawings below.